DESIGN-REUSE
Company
Resume
Design & Reuse (D&R) was founded as a web portal for disseminating value-added information on electronic virtual components, specifically IP (intellectual property) and SoC (systems-on-chips).
Latest
Advancing Die-to-Die Connectivity: The Next-Generation UCIe IP Subsystem (Cadence Blog - Mayank Bhatnagar, Cadence)
October 21, 2024
In today’s evolving AI/ML and HPC/datacenter landscapes, die-to-die connectivity is essential for achieving high-performance and efficient data transfer.
Cadence has achieved a significant milestone with the successful tapeout of its 32G UCIe standard package IP subsystem on TSMC’s 3nm (N3P) process technology.
Designed to advance the performance, power efficiency, and integration of die-to-die connectivity, the subsystem features a comprehensive range of advanced capabilities, setting a new standard in ultra-fast, high-performance interconnect solutions.
Building o
October 21, 2024
In today’s evolving AI/ML and HPC/datacenter landscapes, die-to-die connectivity is essential for achieving high-performance and efficient data transfer.
Cadence has achieved a significant milestone with the successful tapeout of its 32G UCIe standard package IP subsystem on TSMC’s 3nm (N3P) process technology.
Designed to advance the performance, power efficiency, and integration of die-to-die connectivity, the subsystem features a comprehensive range of advanced capabilities, setting a new standard in ultra-fast, high-performance interconnect solutions.
Building o
Profile last updated on October 10th, 2024